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1 standard products ut01vs33l voltage supervisor data sheet july 28, 2014 www.aeroflex.com/voltsupv features ? 3.15v to 3.6v operating voltage range ? power supply (v dd ) monitor set by the internal voltage reference at 3.08v ? precision input voltage monito r using an internal 0.6v voltage reference ? watchdog timer circuit monitoring activity on wdi input - nominal timeout 1.6s ? reset output responding to the v dd monitor and the manual reset input mr - nominal reset pulse width 200ms ? reset level valid for v dd >=1.2v ? operating temperature range -55 o c to +125 o c ? low power, typical 400ua ? operational environment: - total dose: 300 krad(si) - sel immune: < 110 mev-cm 2 /mg @125 o c - set immune: < 80 mev-cm 2 /mg ? packaging options: - 8-lead dual-in-line flatpack ? standard microelectronics drawing 5962-11213 - qml q and v introduction the ut01vs33l?s function is to monitor vital supply and signal voltages in microprocessor systems. it provides for safe reset during power up, power down and brownout conditions by using an internal precisi on voltage reference. the ut01vs33l monitors activity at an independent watchdog input by employing an internal timer and a watchdog output that goes low if the input is not toggled within 1.6s. it provides for precision voltage threshold detection on an independent voltage input which could be used for battery or supply-low monitoring of a supply voltage other than v dd . the ut01vs33l includes an active low manual reset with a push- pull output. applications ? voltage supervisor function for various systems including microprocessors, microcontrollers, dsps and fpgas ? critical battery and power supply monitoring ? replacement of older discrete solutions to improve reliability, accuracy and reduce comp lexity of the systems figure 1. ut01vs33l functional block diagram mr vdd wdo reset ? & digital ? control wdi ? timer wdi ? transition detector osc vref \ + + \ reset wdi pfo gnd pfi 3.08 ? v 0.6 ? v
2 pin descriptions number pins type description 1mr digital input manual reset input with an internal pull-up. active low. mr low forces the reset output reset low. required minimum mr pulse width is 150ns. rese t is held low for duration of the reset timer. 2vddsupply power supply . operating voltage range is 3.15v to 3.6v. v dd level is monitored internally by a dedicated comparator circ uit, which employs an internal bandgap voltage reference nominally equal to 1.25v. every time v dd falls below the threshold voltage, nominally 3.08v, reset and wdo outputs are forced low. (see wdo and reset descriptions.) (figure 4.) 3gndsupply ground. this pin should be tied to ground and establishes the reference for voltage detection. 4 pfi analog input threshold detector input. voltage on this input is fed directly to an internal comparator where it is compar ed to the voltage reference of 0.6v. it can be used for detection of low battery or power failure of voltage supplies other than v dd . when voltage at pfi input drops below its threshold value of 0.6v, pfo output is forced low, otherwise, stays high. 5pfo digital output threshold detector output. active low push-pull output driver. it responds directly to pfi input. if pfi voltage is below the bandgap reference voltage, pfo is low. if pfi is above the reference voltage, pfo output is high. 6 wdi digital input watchdog timer input pin. this pin is typically used to monitor microprocessor activity. it can assume three states: low, high and float. if wdi is floating or connected to a high impedance three state buffer, the watchdog timer is not active, and the corresponding watchdog output wdo is high. watchdog timer is also not active any time reset is low. providing that reset is not asserted, any ch ange of state at wdi that is longer than 100ns will start the timer, or restart it, if the timer is already running (figure 3.). if there is no activity within the timeout period, nominally 1.6s, the timer will stop running and wdo output will go low (figure 3). 7 reset digital output reset output. active low push-pull output driver. this pin is pulled up with a resistor consistant with the sink and voltage current as specified in the el ectrical characteristics table. this output responds to both: v dd monitoring circuits and the manual reset input mr . on power up, reset is guaranteed to be logic low for all v dd values from 1.2v up to the reset threshold, nomi nally 3.08v. once this thresh old is reached, an internal reset timer is activated. during the countdown reset output is kept low. it is raised high upon completion of countdown, typically after 200ms. if a brown out condition occurs during the reset timer countdown, the reset timer would be reset and another countdown would start after v dd levels were restored above the reset threshold. on power down, when v dd falls below the threshold voltage, reset goes low and is guaranteed to stay low until v dd drops below 1.2v. if mr is asserted low, reset is forced low and the reset timer is kept reset. when mr is released high, the ti mer is activated and reset is kept low until completion of the reset timeout, when it is raised high.
3 number pins type description 8wdo digital output watchdog output. active low push-pull output driver. this pin is usually connected to a non-maskable interrupt input of a microprocessor. on power up, wdo responds to v dd monitoring circuitry. it stays low until the reset threshold, 3.08v nominally, is reached. at that point, wdo is raised high. the internal watchdog timer is activated after reset is released. if there is no activity on wdi input, wdo goes low after the watchdog timer times out, which is typically after 1.6sec. any activity on wdi will force wdo output to go high and the watchdog timer will be activated. if wdi is floating or connected to a high impedance buffer output, the timer is kept in a reset state and wdo stays high. when vdd drops below 3.08v, wdo goes low regardless of whether the watchdog timer has timed out or not. reset goes low simultaneously which prevents an interrupt. if wdi input is left unconnected, wdo can be used as a low line output. since a floating wdi disables the internal watchdog timer, wdo goes low when v dd drops below 3.08v, thus, functioning as a low line output. (figure 4.) figure 2. ut01vs33l pin configuration mr vdd gnd pfi wdo reset wdi pfo 1 2 3 4 8 7 6 5 ut01vs33l
4 operational environment absolute maximum ratings 1 (referenced to gnd) notes: 1. stresses outside the listed absolute maximu m ratings may cause permanent damage to th e device. this is a stress rating only, and functional operation of the device at these or any other conditio ns beyond limits indicated in the operational sections of this specification is not r ecommended. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. recommended operating conditions parameter limit units total ionizing dose (tid) 300 krad(si) single event latchup immune (sel) < 110 mev-cm 2 /mg single event tran sient immune (set) < 80 mev-cm 2 /mg symbol parameter limits units v dd voltage supply 7.2 v t j maximum junction temperature 175 ? c t storage temperature -65 to +150 ? c p d power dissipation 2.5 w v in input voltages -0.3v to (v dd +0.3v) v t iead lead temperature (soldering, 10 seconds) +300 ? c ? jc thermal resistance, junction-to-case 15 ? c/w v esd esd hbm 1000 v symbol parameter limits units v dd positive supply voltage 3.15 to 3.6 v t c case temperature range -55 to +125 ? c gnd negative supply voltage 0.0 v
5 electrical characteristics 1,2 (v dd = 3.15v to 3.6v: -55c < t c < +125c) symbol parameter condition min max unit power supply i dd v dd supply current v dd =3.6v 450 ? a digital inputs and outputs (mr , reset , wdi, wdo , pfo ) v il_wdi digital input low v dd =3.15v 0.6 v v ih_wdi digital input high v dd =3.6v 0.7xv dd v v il_mr manual reset input low v dd =3.15v 0.6 v v ih_mr manual reset input high v dd =3.6v 0.7xv dd v v ol_wdo digital output low v dd =3.15v, i sink = 500 ? a0.3v v ol _ reset reset digital output low v dd =3.15v, i sink =1.2ma 0.3 v v ol_pfo pfo digital output low v dd =3.15v, i sink =1.2ma 0.3 v oh 3 digital output high v dd =3.15v, i source =500 ? a 0.8xv dd v timing and threshold voltages t rst-assrt 4 v dd falling reset assertion v dd < 3.0v 0.7 1.8 ? s t rs reset pulse width v dd =3.15v 140 280 ms t wd watchdog time-out period v dd =3.6v 1.0 2.25 s t wp watchdog input pulse width v dd =3.15v 100 ns v rt reset threshold voltage v dd =3.15v 3.0 3.15 v v rthys reset threshold voltage hysteresis 20 mv t mr manual reset (mr ) input pulse width v dd =3.15v 150 ns t md manual reset (mr ) to reset out delay v dd =3.15v 100 ns analog input pfi i pfi 4 threshold detector input (pfi) current v dd =3.6v -20 20 na v pfi threshold detector input (pfi) threshold voltage v dd =3.3v 0.576 0.624 v i mr manual reset pull-up current v dd =3.6v, mr =0.0v -250 -25 ? a t rpfi pfi rising threshold crossing to pfo delay 20 ? s t fpfi pfi falling threshold crossing to pfo delay 40 ? s i wdi watchdog input current wdi pin = v dd = 3.6v wdi pin = 0v, v dd = 3.6v -20 20 ? a ? a
6 notes: 1. for devices procured with a tota l ionizing dose tolerance guarantee, the post-irradiation performance at 25 o c per mil-std-883 method 1 019, condition a, up to the maximum tid level procured (see ordering information). 2. unless otherwise specified, v dd = 3.15v to 3.6v, -55 ? c < t c < +125 ? c. reset is the only parameter operable with in 1.2v and the minimum recommended operating supply voltage. 3. v oh characterization applies to wdo , pfo and reset . 4. guaranteed by design, but not tested.
7 gnd 3.08v v dd vdd gnd v dd reset gnd v dd mr gnd v dd wdo t md t mr t rs 3.08v t wd t wd wdi v dd gnd t rst _ assrt t rs figure 3. wdi and wdo timing waveforms. reset externally triggered by mr figure 4. reset and wdo are driven low fo r vdd <3.08v. wdo is driven high when mr is low gnd v dd wdi gnd v dd wdo t wp t wd t wd t wd reset t rs gnd v dd t md mr v dd gnd t mr
8 shown in figure 5 is an application for monitoring the under voltage of a power supply connected to a microprocessor or asic. if the analog voltage monitored falls belo w the desired threshold value, the pfo output connected to the mr input will transition low causing the reset output to be asserted low indicating an under voltage condition. shown in figure 6 are two voltage supervisors configured to m onitor both the 1.8v and 1.2v power supplies of a system. the 1.8v regulated supply is monitored by the pfi pin of the top vo ltage supervisor, while the 1.2v regulated supply is monitored b y the pfi pin of the bottom voltage supervisor. the cross coupled connection of pfo to mr assures that reset will be asserted when a brown out occurs on either the 1.8v or 1.2v regulated supplies. figure 5. ut01vs33l under voltage monitor and detection 1 2 vdd pfi 3 7 6 8 wdi r1 r2 gnd 4 5 vdd i/o up vdd ? 3.3v vth= ? (r1+r2)/r2 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 50mv vin_analog reset mr wdo pfo reset figure 6. under voltage monitoring and sequ encing of 1.8v and 1.2v power supplies vth= ? (r1+r2)/r2 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 25mv vth= ? (r3+r4)/r4 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 25mv mr 1 2 vdd pfi 3 7 6 8 wdi wdo reset r1 r2 gnd 4 pfo 5 1.8v_reg vout vin en vreg ? 1.8v vout vin en vreg ? 1.2v 1.2v_reg vdd_3.3v mr 1 2 vdd pfi 3 7 6 8 wdi wdo reset gnd 4pfo5 r3 r4 ut01vs33l wdi ? open 1.8v ? reg led r6 1.2v ? reg led r7 vdd_io vdd rstb 3.3v ? and ? gate ut01vs33l/d
9 shown in figure 7 is an application to monitor and detect power supply over voltage through the use of the pfi pin. when the voltage at the pfi input, (vth ) exceeds vref, (0.6v) the pfo output transitions from low to high causing the mr output to transition from high to low. this asserts a reset indicating the voltage being monitored has exceeded the over voltage monitor limit. figure 7. ut01vs33l over voltage po wer supply monitoring and reset vdd i/o resetb up mr 1 2 vdd pfi 3 7 6 8 wdi wdo reset r1 r2 gnd 4 pfo 5 ut01vs33l vth_ov= ? (r1+r2)/r2 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 25mv vdd ? 3.3v 3.3v ? inv ? gate in1
10 shown in figure 8 is an application using two ut01vs33l voltage supervisors to monitor both unde r voltage and over voltage of a power supply. in this application the top voltage supervisor monitors the under-voltage of a 3.3v power supply while the bot tom voltage supervisor monitors the over voltage of the same 3.3v power supply. the 3.3vsupply is monitored through the pfi input of both voltage supervisors. resistor values for both under voltage and over voltage monitoring can be set to accommoda te a range of power supply voltages. during normal operation where vdd is within the allowed range (vdd_und < vdd < vdd_ov), reset of both voltage supervisors will be at logic high level. the table 1 below shows the truth table for functional, under voltage detection and o ver voltage detection. figure 8. ut01vs33l under voltage and over voltage power supply monitoring and reset mr 1 2 vdd pfi 3 7 6 8 wdi wdo reset r1 r2 gnd 4 pfo 5 vdd i/o resetb up mr 1 2 vdd pfi 3 7 6 8 wdi wdo reset r3 r4 gnd 4 pfo 5 i/o resetb ut01vs33l under ? voltage ? monitor ut01vs33l over ? voltage ? monitor vdd ? 3.3v 3.3v ? inv ? gate in1 vth_ov= ? (r1+r2)/r2 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 25mv vth_ov= ? (r3+r4)/r4 ? ) ? * ? vpfi vpfi=0.6v ? +/ \ 25mv
11 notes : -und specifies under voltage case. -ov specifies overvoltage case table 1. under voltage ov er voltage truth table vdd pfo _und pfo _ov reset _ und reset _ ov reset up or asic mode normal operation high low high high high normal vdd < vdd_und low low low high low reset asserted vdd > vdd_ov high high high low low reset asserted
12 figure 9. 8-pin du al-in-line flatpack
13 ordering information ut01vs33l voltage supervisor lead finish: (notes: 1) (c) = gold screening level: (notes: 2 and 3) (p) = prototype flow (c) = hirel flow (temperature range -55 o c to +125 o c) case outline: (x) = 8-lead ceramic flat package tid tolerance: (-) = none device type (l) = active low reset generic part number: (01vs33) ut ****** * - * * * notes: 1. lead finish is "c" (gold) only. 2. prototype flow per aeroflex manufacturing flows document. devices are tested at 25 ? c only. lead finish is gold "c" only. radiation neither tested nor guaranteed. 3. hirel flow per aeroflex manufacturing flows do cument. radiation neither tested nor guaranteed.
14 ut01vs33l voltage supervisor: smd lead finish: (note: 1) (c) = gold case outline: (x) = 8-lead ceramic flatpack screening level: (q) = qml class q (v) = qml class v device type: (15) = ut01vs33l (temperature range: -55 o c to +125 o c) drawing number: 11213 = 3.3v single channel voltage supervisor total dose: (r) = 100 krad(si) (f) = 300 krad(si) federal stock class number: no options 5962 * ***** ** * * * notes: 1. lead finish is ?c? (gold) only.
15 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export un der the international traffi c in arms regulations (itar). a license from the u.s. government is required prior to the export of this product from the united states. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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